TxClk_DF=TxClk_DF_0, SYSCLK_DF=SYSCLK_DF_0, tx_all_clk_en=tx_all_clk_en_0, TxClk_Source=TxClk_Source_0
SPDIFTxClk Register
| TxClk_DF | Divider factor (1-128) 0 (TxClk_DF_0): divider factor is 1 1 (TxClk_DF_1): divider factor is 2 127 (TxClk_DF_127): divider factor is 128 |
| tx_all_clk_en | Spdif transfer clock enable. When data is going to be transfered, this bit should be set to1. 0 (tx_all_clk_en_0): disable transfer clock. 1 (tx_all_clk_en_1): enable transfer clock. |
| TxClk_Source | no description available 0 (TxClk_Source_0): REF_CLK_32K input (XTALOSC 32 kHz clock) 1 (TxClk_Source_1): tx_clk input (from SPDIF0_CLK_ROOT. See CCM.) 3 (TxClk_Source_3): SPDIF_EXT_CLK, from pads 5 (TxClk_Source_5): ipg_clk input (frequency divided) |
| SYSCLK_DF | system clock divider factor, 2~512. 0 (SYSCLK_DF_0): no clock signal 1 (SYSCLK_DF_1): divider factor is 2 511 (SYSCLK_DF_511): divider factor is 512 |